A Phase Locked Loop (PLL) is an electrical circuit usable to generate a synthesized oscillating signal that matches a reference signal. The synthesized oscillating signal is considered to be “locked” with the reference signal when the frequency and/or phase of the synthesized oscillating signal and that of the reference signal are substantially the same. In some applications, such as in a radio frequency synthesizer circuit, the frequency of the synthesized oscillating signal is so high that direct comparison of the synthesized oscillating signal and the reference signal is technically and/or economically infeasible. Under these circumstances, a divider or a prescaler may be used to generate a pre-scaled feedback signal obtained by dividing the synthesized oscillating signal by a factor N. The pre-scaled feedback signal is a “snap shot” of the synthesized oscillating signal having a frequency which is 1/N of that of the synthesized oscillating signal. The synthesized oscillating signal is then considered to be “locked” with the reference signal when the frequency and/or phase of the pre-scaled feedback signal and that of the reference signal are substantially the same.